Semiconductor memory cells are well known and have been used extensively for many years to store a single bit of binary data as a "1" or "0". Unfortunately, the data bit stored in the cell can be corrupted if the cell is exposed to an ionized particle such as an .alpha. particle, T, Ma and P. Dressendorfer, Ionizing Radiation Effects in MOS Devices & Circuits, New York, NY, John Wiley & Sons, 1989, Chapter 9. Current induced by a particle hit flows from an n-type diffusion to a p-type diffusion. Thus, a "1" can be upset in an NMOS static RAM cell and a "0" can be upset in a PMOS static RAM cell.
A variety of techniques have been employed to attempt to prevent the data stored in a cell from inadvertently changing states even when the cell is struck by a charged particle. For example, Japanese patent 62-154296, issued on July 9, 1987 and invented by Honjo and Japanese patent 57-12486, issued on Jan. 1, 1982 and invented by Yoshimoto each teach coupling a capacitor between the drains of the two storage transistors. Because the voltage across a capacitor cannot change instantaneously, the two nodes will track one another in the event that there is an exposure to a charged particle. In the event that the voltage excursion due to the charged particle is of sufficiently short duration, the state of the cell will not change inadvertently.
In another approach, the transistor count in the basic cell is doubled, L. Rockett, An SEU Hardened CMOS Data Latch Design, IEEE Transactions on Nuclear Science, Vol. 35, No. 6, pp. 1682-1687, Dec., 1988. While, the data is stable, the loading seen by the clock signal in a circuit built according to the Rockett paper is such that the circuit performance is degraded.
A static RAM design is needed which is immune to a SEU and which provides acceptable performance.